This paper proposes an area-efficient fast Fourier transform (FFT) processor for zero-padded\nsignals based on the radix-2^2 and the radix-2^3 single-path delay feedback pipeline architectures.\nThe delay elements for aligning the data in the pipeline stage are one of the most complex units\nand that of stage 1 is the biggest. By exploiting the fact that the input data sequence is zero-padded\nand that the twiddle factor multiplication in stage 1 is trivial, the proposed FFT processor can\ndramatically reduce the required number of delay elements. Moreover, the 256-point FFT processors\nwere designed using hardware description language (HDL) and were synthesized to gate-level\ncircuits using a standard cell library for 65 nm CMOS process. The proposed architecture results in a\nlogic gate count of 40,396, which can be efficient and suitable for zero-padded FFT processors.
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